CMOS ASIC Converting FPGAs and PLDs to Atmel Gate Arrays Introduction Atmel is one of the only companies that designs and manufactures field programmable gate arrays (FPGAs), programmable logic devices (PLDs) and high performance gate arrays. Atmel offers a seamless, direct conversion path for designs implemented on most PLDs and FPGAs to its gate array families. The potential benefits to the system designer of such a capability are fourfold: * Component cost savings. Atmel's conversion process will convert a single FPGA or PLD into a lower cost gate array that is a pin-for-pin compatible replacement. * Board space savings. Atmel converts to a true gate array, not a hardwired FPGA/PLD. Multiple FPGAs or PLDs can be converted and consolidated into a single gate array, reducing system component count and providing even more cost savings. * Enhanced performance. Conversion to a gate array grants the designer access to all of the macrocells and functions contained in the cell library. Included are higher order logic functions, inclusion of SRAM, PCI and other buffers and testability improvement circuitry that cannot be realized on an FPGA or PLD. Gate array routing schemes allow a greater degree of flexibility to optimize timing performance or logic area. * Reduction in design cycle time. An ASIC design can be prototyped using programmable logic and migrated to a gate array for production without the time and cost of a re-design. In all cases, Atmel uses the existing FPGA or PLD design database so that little additional engineering effort is required from the customer. This application note discusses some factors to consider when deciding to convert, describes the conversion process, and details the required information for selected FPGA and PLD products. FPGA/PLD to Gate Array Conversion Application Note Converting FPGAs and PLDs to Atmel Gate Arrays 0145D 9-99 ATL50 Array Organization - 0.5m CMOS Device Number Raw Gates Routable Gates Max Pin Count Max I/O Pins Gate (1) Speed ATL50/4 4,000 3,000 44 36 200 ps ATL50/15 15,000 10,000 68 60 200 ps ATL50/25 25,000 16,900 84 76 200 ps ATL50/40 38,000 25,400 100 92 200 ps ATL50/60 58,000 34,600 120 112 200 ps ATL50/85 86,000 51,900 144 136 200 ps ATL50/110 110,000 65,900 160 152 200 ps ATL50/150 149,000 89,300 184 176 200 ps ATL50/200 195,000 116,900 208 200 200 ps ATL50/235 232,000 139,500 226 218 200 ps ATL50/300 301,000 181,000 256 248 200 ps ATL50/435 430,000 260,000 304 296 200 ps ATL50/550 545,000 288,000 340 332 200 ps ATL50/700 693,000 363,000 380 372 200 ps ATL60/870 870,000 456,000 424 416 200 ps ATL60/1100 1,119,000 590,000 480 472 200 ps Routable Gates Max Pin Count Max I/O Pins Gate(1) Speed Notes: 1. Nominal 2-input NAND gate with a fan out of two at 3.3 volts. ATL60 Array Organization - 0.6m CMOS Device Number Raw Gates ATL60/4 4,000 3,000 44 36 200 ps ATL60/15 15,000 10,000 68 60 200 ps ATL60/25 25,000 16,900 84 76 200 ps ATL60/40 38,000 25,400 100 92 200 ps ATL60/60 58,000 34,600 120 112 200 ps ATL60/85 86,000 51,900 144 136 200 ps ATL60/110 110,000 65,900 160 152 200 ps ATL60/150 149,000 89,300 184 176 200 ps ATL60/200 195,000 116,900 208 200 200 ps ATL60/235 232,000 139,500 226 218 200 ps ATL60/300 301,000 181,000 256 248 200 ps ATL60/435 430,000 260,000 304 296 200 ps ATL60/550 545,000 288,000 340 332 200 ps ATL60/700 693,000 363,000 380 372 200 ps ATL60/870 870,000 456,000 424 416 200 ps ATL60/1100 1,119,000 590,000 480 472 200 ps Notes: 1. Nominal two input NAND gate with a fan out of two at 5.0 volts. 9-100 CMOS ASIC CMOS ASIC ATLS60 Array Organization Device Number Raw Gates Routable Gates Max Pin Count Max I/O Pins Gate(1) Speed ATLS60/80 12,500 8,000 80 72 200 ps ATLS60/100 20,400 13,000 100 92 200 ps ATLS60/120 30,200 17,500 120 112 200 ps ATLS60/144 44,600 26,000 144 136 200 ps ATLS60/160 55,300 32,500 160 152 200 ps ATLS60/208 96,500 57,000 208 200 200 ps ATLS60/225 113,500 67,500 225 217 200 ps ATLS60/256 148,200 88,000 256 248 200 ps Note: 1. Nominal 2 input NAND Gate with a Fan Out of 2 Programmable Logic vs Gate Array Why Convert? Programmable logic devices have enjoyed tremendous popularity and growth over the last several years, primarily because the user saves both time and money. Designers may work with multiple design tools that run on inexpensive platforms. Designs can be implemented in hours and modified easily, allowing for system performance evaluation in the same week. This instant feedback allows designers to validate system operation and rectify any errors without additional expense. Programmable logic devices provide an ideal solution for low to moderate production volumes and for fast prototyping of more complex logic designs. As volumes increase, however, programmable devices may become prohibitively expensive. There are four instances when converting from a programmable logic device to a gate array offers the user a direct benefit. Gate arrays provide an efficient implementation of the design. They offer superior performance, higher density, and lower cost-per-gate in production volumes when compared to programmable logic devices. Design tools that support gate arrays are typically more comprehensive and expensive than FPGA/PLD design tools. However, many ASIC design platforms now support FPGA design. The ability to simulate both the programmable device and the gate array in the same design environment allows the designer to compare and verify the conversion. However, while gate array prototypes can be delivered in days or weeks, that is still a much longer period than the verification cycle of a programmable logic device. Gate array designs typically require a nonrecurring expense for design implementation, and design revisions may require additional time and expense. Save Money at High Volumes. If the cost of one year's supply of programmable devices approximates the cost of the nonrecurring expense plus the initial year's supply of a gate array device, serious consideration should be given to conversion. After the nonrecurring expense is amortized, the cost savings become even more dramatic. Time To Market Versus Cost Reduction. Using a programmable device for logic verification and prototyping and then converting to a gate array gives the designer the best of both worlds - a fast, accurate design cycle and a low cost component in production. Higher Performance. Gate arrays have lower standby and operating current, plus offer greater speed than an FPGA/PLD. The designer also has a greater selection of buffer types, drive currents, and a wide selection of higher order logic and memory (SRAM) functions. Integration. Converting several FPGAs or PLDs and consolidating the logic into a single gate array uses less printed circuit board space, reduces the component count, consumes less power, and improves the reliability of the system. 9-101 Converting FPGAs/PLDs Atmel's conversion process is designed to minimize the amount of engineering support required from the system designers, provided the requisite design database is Figure 1. FPGA/PLD to Gate Array Conversion 9-102 CMOS ASIC received. The inputs required vary depending on the original manufacturer of the FPGA/PLD. Figure 1 outlines the conversion process flow. CMOS ASIC The first step toward meeting Data Acceptance (DA) is the submission of the design database to Atmel. If all required elements for DA are present, the design database can quickly be accepted. Frequently issues arise with format of the vectors (or another element) or with missing items which require some work to be done to meet DA. Because Atmel can never be certain what type of database will be received from the customers, all schedules for the design use DA as the starting point. In other words, the clock starts once DA has been met. Once Atmel database acceptance has been met, the original design is converted into an equivalent netlist using the Atmel cell library via Synopsys . Synopsys tools can read a variety of formats, including our preferred formats of EDIF and Verilog . Figure 2 outlines the process by which synopsys converts the FPGA netlist into Verilog-XL format. The database is input to a proprietary Atmel mapping file for translation into Atmel cells. When the design is mapped in its entirety, a Verilog netlist in Atmel cells is produced. The equivalent netlist ensures that both the functionality and timing of the new design match the original. Using this technique, almost any FPGA/PLD design can be converted to a gate array. Figure 2. FPGA Conversion Verilog Netlist FPGA Netlist (EDIF) Mapping File Synopsys Hierarchical Verilog Netlist Synopsys Flattened Verilog Netlist Verilog Netlist in Atmel Cells 9-103 The original test vectors are also converted and are used to verify the gate array design. Good functional vectors must be provided or developed. This is important because the functional test vectors are the verification vehicle for the new gate array design. The final approval of the vectors to be used falls upon the original designer; one is better served to produce and verify the test vectors prior to database submission than to attempt to reconstruct them after the fact. All vectors must be in the same five groups (Input, Output, Tri-state , Bi-directional, and Enable) and have a stated purpose. Outputs are sampled once per clock cycle at the 75% cycle point. Test vectors must include a 1 MHz set for wafer probe and an "at speed" set for final test. "At speed" may be a 1 MHz set with certain critical paths identified for testing "at speed". Test vectors must pass Atmel's Test Vector Checker (tvc), a tool provided with our libraries to verify the format of the vector set. Design data base formats, simulation/test vector formats, specifications, and documentation requirements are listed below. Required Database Design Database Format - EDIF 2.0.0 - Synopsys .db files - Verilog structural netlist - Xilinx .xnf files The source cell library is: - Actel FPGA - Altera FPGA/PLD - Atmel FPGA - Xilinx FPGA - Other Simulation/Test Vector Format - ALTERA Format ASCII Tabular Format COMPASS Tabular Trace Format ORCAD Format Quicksim Logfile Format Quicksim List Format Verilog Format VIEWlogic Tabular Format VLAIF Tabular Format Specifications - Operating conditions of voltage and temperature System loading requirements by pin Operating clock speed and number of clocks I/O definition including pin out and enable for Tri-state and bi-directional buffers - Identification of critical paths - Definition of asynchronous behavior 9-104 CMOS ASIC Documentation - Full hierarchical schematics - Clock tree and reset diagram - Timing diagrams showing relationship of clocks to data applied and valid outputs After the design has been converted and verified for functional performance, the optimization process begins. The design can be optimized to match the timing performance of the original FPGA/PLD design or to meet new performance goals. Additional logic functions or memory can be added to the gate array as well. Before physical design of the chip begins, a joint Preliminary Design Review is held with Atmel and the customer to approve the results of the converted design. From this point on, the design process is identical to that of a traditionally designed gate array. The design is physically placed and routed on the gate array and verified for electrical and design rules. Atmel uses Cadence's Verilog-XL as a golden simulator. Atmel guarantees performance equal to or better than that predicted by Verilog-XL post route simulation. Back annotation data is extracted from the actual layout and incorporated into the post-route functional and timing simulation. Minor layout modifications may be required to meet the timing specification. A Final Design Review is held to approve the post-route simulation data. After customer approval, the design is released for mask generation and prototyping. Prototypes can be delivered in as little as three weeks and production units in as short as six weeks after customer approval of prototypes. Atmel guarantees the gate array will be a pin-for-pin compatible replacement for the FPGA/PLD. Tables 1-5 list the recommended Atmel gate arrays for conversion from various Actel , Altera , Xilinx , Cypress , and Lattice programmable devices. Gate Array Implementation After database acceptance, the design database is converted into an equivalent netlist of primitive cells from Atmel's gate array library. The vectors from the original FPGA or PLD design are also converted and are used as functional simulation vectors to validate the gate array netlist. As these vectors are used to perform any timing simulation and form the core of the gate array tester program, it is vitally important that an accurate and complete vector set is provided. After the FPGA or PLD databases have been converted and validated, any additional circuitry, such as memory blocks, testability improvement elements, or higher order logic functions, can be incorporated into the netlist. Any optimization that is necessary to match timing or to improve performance can be performed at this point as CMOS ASIC well. At this point, boundary and internal scan can be added and ATPG vectors generated. A Preliminary Design Review is then held with the customer to review and to approve the results of the design conversion. Preliminary Design Review (PDR) The following items are reviewed at the PDR: * Confirm Netlist Checker (v3) and Test Vector Checker (tvc) files correct * I/O buffer listing and bonding diagram * Preliminary testability compiler report * Route clock tree and analysis of worst case and best case delay * Verilog simulation at-speed -nominal, worst case, best case (with no timing violations) * Review critical path information (tSU, tHOLD, tPD) -Verilog or Veritime estimates * I/O electrical specifications * Electromigration calculation Final Design Review (FDR) Beyond this point, the design process follows that of a traditionally designed gate array. The cells are placed and routed, a post-route simulation is performed, and checks are performed to verify conformance with electrical and design rules, and to confirm the Logic Versus Schematic (LVS) is correct. An FDR is held with the customer to review and approve the post route data, and to authorize mask making and prototype fabrication. The FDR is the last joint review between Atmel and the customer before committing to prototypes. Prior to this meeting, both Atmel and the customer will have reviewed the post-route Verilog-XL simulation incorporating the back annotation data. The customer may receive back annotation data for complete post-route simulation on their CAE systems. Atmel guarantees silicon performance equal to or better than that predicted by the post-route Verilog-XL simulations. The items to be reviewed at FDR are as follows: * Updates of cell mapping and timing (if any) * Post-route netlist check (v3) -post-route netlist changes * Post-route timing simulation to specification -review clock timing -at speed -clock skew (if required) -listing of timing warnings with explanation * Static path analysis (as specified) * Electromigration calculation * Bonding diagrams and pin list -bond pad plot * LVS/DRC/ERC Prototype Delivery Atmel will deliver 10 prototypes in ceramic or TQFP packages to the customer. The units are to verify the functionality and electrical performance of the gate array. Synthesis from a Hardware Description Language (HDL) There has been an increase in the use of HDLs to design FPGAs and PLDs as more of the design platforms offer this capability. Two of the most popular languages are VHDL and Verilog-HDL. Using a logic synthesis technique, the behavioral level description of an FPGA or PLD can be mapped into a functionally equivalent gate array netlist. Both hardware description languages are supported by the Synopsys Design Compiler. This FPGA/PLD to gate array conversion methodology requires the least amount of data conversion and allows the flexibility to incorporate such features as memory, testability, or higher order logic functions into the gate array. This technique is also effective when the need to consolidate several FPGA or PLD designs into one gate array exists. Synthesis from an HDL offers the most efficient utilization of the gate array, at the expense of timing matching. Should the user require them, VHDL descriptions of the converted FPGAs or PLDs, as well as the gate array implementation, can be provided by exporting the netlists through Synopsys. Testability Improvement and Automatic Test Pattern Generation The incorporation of testability improvement circuitry into an ASIC design becomes more important as the density of the design increases. The same can be said for conversion and consolidation of large numbers of dense FPGAs or PLDs into a gate array. The insertion of scan paths within an ASIC and testing via ATPG can provide an easy means of screening manufacturing-related defects during testing, with a relatively small silicon usage penalty. Using ATPG is only a supplement to functional test vectors, not a replacement. The process consists of replacing existing flip-flops with scan flip-flops and connecting them up to form scan chains. An input pin and output pin must be identified for each scan chain. In general, scan chains should not exceed 64 flip-flops in length. Thus, for a design with 600 flip-flops, 10 input pins and their corresponding output pins must be identified. Existing pins may be multiplexed for this use if the design is pin limited. Additional pins are required for the Test Enable (TE) signal and a Test Mode (TM) signal. The TE pin is used to control the flip-flops, placing them in either normal mode or scan mode. 9-105 The TM pin is required to bypass violations of testability guidelines, an example of which would be gated clocks. During testing, all flip-flops in the scan chains must toggle on the same clock. If gated clocks exist in the design, logic must be designed so that it bypasses this gating when Test Mode is active. Since Test Mode is active only during ATPG test, the basic function of the design is unaffected. The Synopsys Test Compiler Guidelines table outlines other testability rules and suggested workarounds utilizing the Test Mode signal. When all test guidelines are followed, testability insertion and vector generation are easily accomplished. Past experience has shown extremely high fault coverage (up to 99%) with small ATPG vector sets. If these rules are not followed closely, incorporating scan and ATPG can require several weeks. It is highly recommended that the FPGA be designed using the rules in Table 6 if the customer intends to someday convert to a gate array and use scan/ATPG. Synopsys Test Compiler Guidelines Testability Rule Effects of Infraction Work around Synchronous Design - No cross coupled gates - No unregistered feedback Associated logic untestable Break feedback path with test mode Single Edge Clocking Clocked device not allowed in scan chain - reduced fault In test mode, create single edge clocking with inverters and MUXs No Clock Gating Clocked device not allowed in scan chain - reduced fault coverage Use data disable flip-flops instead of clock enables, disable gating in test mode No Latches Not allowed in scan chain, reduced fault coverage Use alternate test methods, force latches to transparent mode with test mode Single External Reset - No asynchronous resets or presets generated on chip - No combinational logic in reset path Not allowed in scan chain, reduced fault coverage Reset OR'd with test mode No Internal Tri-state Buses Reduced fault coverage, possible Tri-state contention during scan test Use MUXs or AOI gates, insert gating of controls to prevent contention No Direct Q to D Connections Dynamic Hazard 9-106 CMOS ASIC CMOS ASIC Table 1. Xilinx(R) FPGA/CPLD/Atmel Gate Array Cross Reference Xilinx(R) Target Atmel Gate Array(1) Equivalent Usable Gates I/O Pins ATLS60 Series XC2064 XC2064L 1000 58 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 XC2018 XC2018L 1500 74 ATLS60/80 ATLS60/100 ATL60/15 ATL60/25 ATL50/15 ATL50/25 XC3020A XC3020L 1500 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 XC3030A XC3030L 2000 100 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 XC3042A XC3042L 3000 144 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 XC3064A XC3064L 5000 224 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 XC3090A XC30090L 6000 320 ATL60/435 ATL60/550 ATL50/435 ATL50/550 XC3120A 1500 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 XC3130A 2000 80 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 XC3142A XC3142L 3000 96 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 XC3164A 4500 120 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 XC3190A XC3190L 6000 144 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 XC3195A 7500 176 ATLS60/160 ATLS60/208 ATL60/150 ATL50/150 XC4003E 3000 80 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 XC4005E XC4005L 5000 112 ATLS60/120 ATL60/60 ATL50/60 XC4006E 6000 128 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 XC4008E 8000 144 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 XC4010E XC4010L 10000 160 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 XC4013E XC4013L 13000 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 XC4020E 20000 224 ATLS60/208 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 FPGA Note: ATL60 Series ATL50 1. Target array dependent on number of I/O pins used, and pinout. 9-107 Table 1 (continued). Xilinx(R) FPGA/CPLD/Atmel Gate Array Cross Reference Xilinx(R) Target Atmel Gate Array(1) FPGA Equivalent Usable Gates I/O Pins ATLS60 Series XC4025E 25000 256 ATLS60/256(2) ATL60/300 ATL60/435 ATL50/300 ATL50/435 XC4028EX XC4028LX 28000 256 ATLS60/256(2) ATL60/300 ATL60/435 ATL50/300 ATL50/435 XC4036EX XC4036LX 36000 288 ATL60/300 ATL60/435 ATL50/300 ATL50/435 XC4044EX XC4044LX 44000 320 ATL60/435 ATL60/550 ATL50/435 ATL50/550 XC4052XL 52000 352 ATL60/550 ATL60/700 ATL50/550 ATL50/700 XC4062XL 62000 384 ATL60/700 ATL60/870 ATL50/700 ATL50/870 XC5202/L 3000 84 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 XC5204 6000 124 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 XC5206/L 10000 148 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 XC5210 16000 196 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 XC5215/L 23000 244 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 XC6209 13000 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 XC6216 24000 256 ATL560/256(2) ATL60/300 ATL60/435 ATL50/300 ATL50/435 XC6236 55000 384 ATL60/700 ATL60/870 ATL50/700 ATL50/870 XC6264 100000 512 ATL60/1100(3) ATL50/1100(3) Note: 9-108 ATL60 Series 1. Target array dependent on number of I/O pins used, and pinout. 2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 248 I/O pins. 3. ATL60/1100 has 472 I/O pins and will only accommodate devices with no more than 472 I/O pins. CMOS ASIC ATL50 CMOS ASIC Table 1 (continued). Xilinx(R) FPGA/CPLD/Atmel Gate Array Cross Reference Xilinx(R) I/O Pins ATLS60 Series XC7236A 30 ATLS60/80 ATL60/4 ATL50/4 XC7272A 42 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 XC7318 17 ATLS60/80 ATL60/4 ATL50/4 XC7336 32 ATLS60/80 ATL60/4 ATL50/4 XC7354 42 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 XC7372 42 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 XC73108 78 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 XC73144 120 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 XC9536 34 ATLS60/80 ATL60/4 ATL50/4 XC9572 69, 72 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 XC95108 69, 81, 108 ATLS60/80 ATLS60/100 ATLS60/120 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL50/15 ATL50/25 ATL50/40 ATL50/60 XC95144 81, 133 ATLS60/100 ATLS60/120 ATLS60/144 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL50/25 ATL50/40 ATL50/60 ATL50/85 XC95180 133, 166 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL50/60 ATL50/85 ATL50/110 ATL50/150 XC95216 133, 166 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL50/60 ATL50/85 ATL50/110 ATL50/150 XC95288 168, 192 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL60/200 ATL50/110 ATL50/150 ATL50/200 XC95432 232 ATLS60/208 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 XC95576 232 ATLS60/208 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 CPLD Note: Equivalent Usable Gates(1) Target Atmel Gate Array(2) ATL60 Series ATL50 1. Equivalent usable gate data not available. 2. Target array dependent on number of I/O pins used, and pinout. 9-109 Table 2. Altera FPGA/PLD/Atmel Gate Array Cross Reference Altera FPGA Flex 10K Flex 8000 Note: 9-110 Target Atmel Gate Array(1) Equivalent Usable Gates I/O Pins EPF10K10 31000 134 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 EPF10K20 63000 189 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 EPF10K30 69000 246 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 EPF10K40 93000 189 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 EPF10K50 116000 310 ATL60/435 ATL60/550 ATL50/435 ATL50/550 EPF10K70 118000 358 ATL60/550 ATL60/700 ATL50/550 ATL50/700 EPF10K100 158000 406 ATL60/700 ATL60/870 ATL50/700 ATL50/870 EPF8282A EPF8282AV 2500 78 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 EPF8452 EPF8452A 4000 120 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 EPF8636A 6000 136 ATLS60/144 ATL60/85 ATL50/85 EPF8820 EPF8820A 8000 152 ATLS60/160 ATL60/110 ATL50/110 EPF81188 EPF81188A 12000 184 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 EPF81500 EPF81500A 16000 208 ATLS60/208 ATLS60/225 ATL60/200 ATL60/235 ATL50/200 ATL50/235 ATLS60 Series 1. Target array dependent on number of I/O pins used, and pinout. CMOS ASIC ATL60 Series ATL50 CMOS ASIC Table 2 (continued). Altera FPGA/PLD/Atmel Gate Array Cross Reference Altera PLD Equivalent Usable Gates I/O Pins EPM9320 6000 168 EPM9400 8000 EPM9480 EPM9560 Target Atmel Gate Array(1) ATLS60 Series ATL60 Series ATL50 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 184 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 10000 200 ATLS60/208 ATL60/200 ATL50/200 12000 216 ATLS60/208 ATLS60/225 ATL60/200 ATL60/235 ATL50/200 ATL50/235 EPM7032 EPM7032V EPM7032S 600 36 ATLS60/80 ATL60/4 ATL50/4 EPM7064 EPM7064S 1250 68 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 EPM7096 EPM7096S 1800 76 ATLS60/80 ATLS60/100 ATL60/25 ATL50/25 EPM7128E EPM7128S 2500 100 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 EPM7160E EPM7160S 3200 104 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 EPM7192E EPM7192S 3750 124 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 EPM7256E EPM7256S 5000 164 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 EPM5032 600 24 ATLS60/80 ATL60/4 ATL50/4 EPM5064 1250 36 ATLS60/80 ATL60/4 ATL50/4 EPM5128 EPM5128A 2500 60 ATLS60/80 ATL60/15 ATL50/15 EPM5130 2500 100 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 RPM5192 3200 104 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 EP610 300 20 ATLS60/80 ATL60/4 ATL50/4 EP910 450 36 ATLS60/80 ATL60/4 ATL50/4 EP1810 900 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 Max 9000 Max 7000 Max 7000S Max 5000 Classic Note: 1. Target array dependent on number of I/O pins used, and pinout. 9-111 Table 3. Actel FPGA/Atmel Gate Array Cross Reference Actel FPGA Integrator Series 1200XL and 3200DX Accelerator Series ACT 1 ACT 2 ACT 3 Target Atmel Gate Array(1) Equivalent Usable Gates I/O Pins A1225XL 2500 83 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 A1240XL 4000 104 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 A3265DX 6500 126 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 A1280XL 8000 140 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 A32100DX 10000 152 ATLS60/160 ATL60/110 ATL50/110 A32140DX 14000 176 ATLS60/160 ATLS60/208 ATL60/150 ATL50/150 A32200DX 20000 202 ATLS60/208 ATLS60/225 ATL60/200 ATL60/235 ATL50/200 ATL50/235 A32300DX 30000 250 ATLS60/256(2) ATL60/300 ATL60/435 ATL50/300 ATL50/435 A32400DX 40000 288 ATL60/300 ATL60/435 ATL50/300 ATL50/435 A1010B A10V10B 1200 57 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 A1020B A10V20B 2000 69 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 A1225A 2500 83 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 A1240A 4000 104 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 A1280A 8000 140 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 A1415 1500 80 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 A1425 2500 100 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 A1440 4000 140 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 A1460 6000 168 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 A14100 10000 228 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 ATLS60 Series ATL60 Series Notes: 1. Target array dependent on number of I/O pins used, and pinout. 2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 248 I/O pins. 9-112 CMOS ASIC ATL50 CMOS ASIC Table 3 (continued). Actel FPGA/Atmel Gate Array Cross Reference Actel FPGA ACT 3 PCI Compliant Note: Equivalent Usable Gates I/O Pins A1440BP 4000 140 A1460BP 6000 A14100BP 10000 Target Atmel Gate Array(1) ATLS60 Series ATL60 Series ATL50 ATLS60/144 ATLS60/160 ATL60/85 ATL60/110 ATL50/85 ATL50/110 168 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 228 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 1. Target array dependent on number of I/O pins used, and pinout. 9-113 Table 4. Lattice PLD/Atmel Gate Array Cross Reference Target Atmel Gate Array(1) Equivalent Usable Gates (PLD Gates) I/O Pins 1016E 2000 36 ATLS60/80 ATL60/4 ATL50/4 1024 4000 54 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 1032E 6000 72 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 1048E 8000 110 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 2032 2032LV 1000 34 ATLS60/80 ATL60/4 ATL50/4 2064 2064LV 2000 68 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 2096 2096LV 4000 102 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 2128 2128LV 6000 136 ATLS60/144 ATL60/85 ATL50/85 3160 7000 160 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 3192 9000 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 3256 11000 128 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 3256E 12000 256 ATLS60/256(2) ATL60/300 ATL60/435 ATL50/300 ATL50/435 3320 14000 160 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 Lattice PLD ATLS60 Series (R) ispLSI 1000/E ispLSI(R) 2000 and ispLSI(R) 2000LV ispLSI(R) 3000 ATL60 Series Notes: 1. Target array dependent on number of I/O pins used, and pinout. 2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 248 I/O pins. 9-114 CMOS ASIC ATL50 CMOS ASIC Table 5. Cypress FPGA/PLD/Atmel Gate Array Cross Reference Cypress FPGA Ulta38000 pASIC380 Note: Target Atmel Gate Array(1) Equivalent Usable Gates I/O Pins CY7C38003 CY7C338003 3000 120 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 CY7C38005 CY7C338005 5000 156 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 CY7C38007 CY7C38007 7000 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 CY7C38009 CY7C338009 9000 228 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 CY7C380012 CY7C3380012 12000 264 ATLS60/256 ATL60/300 ATL60/435 ATL50/300 ATL50/435 CY7C380016 CY7C3380016 16000 300 ATL60/435 ATL60/550 ATL50/435 ATL50/550 CY7C380020 CY7C3380020 20000 336 ATL60/550 ATL60/700 ATL50/550 ATL50/700 CY7C381P CY7C3381A 1000 32 ATLS60/80 ATL60/4 ATL50/4 CY7C382P CY7C3382A 1000 56 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 CY7C383A CY7C3383A 2000 56 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 CY7C384A CY7C3384A 2000 80 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 CY7C385P CY7C3385A 4000 80 ATLS60/80 ATLS60/100 ATL60/25 ATL60/40 ATL50/25 ATL50/40 CY7C386P CY7C3386A 4000 114 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 CY7C387P CY7C3387P 8000 116 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 CY7C388P CY7C3388P 8000 172 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 ATLS60 Series (2) ATL60 Series ATL50 1. Target array dependent on number of I/O pins used, and pinout. 2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 256 I/O pins. 9-115 Table 5 (continued). Cypress FPGA/PLD/Atmel Gate Array Cross Reference Cypress PLD Equivalent Usable Gates(1) I/O Pins ATLS60 Series 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 (160) 128 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 39256 (160) 128 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 (208) 160 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 39320 (208) 160 ATLS60/160 ATLS60/208 ATL60/110 ATL60/150 ATL50/110 ATL50/150 (240) 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 39384 (240) 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 39448 (240) 192 ATLS60/160 ATLS60/208 ATL60/150 ATL60/200 ATL50/150 ATL50/200 (304) 224 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/300 39512 (304) 224 ATLS60/225 ATLS60/256 ATL60/235 ATL60/300 ATL50/235 ATL50/30 371 32 ATLS60/80 ATL60/4 ATL50/4 372 32 ATLS60/80 ATL60/4 ATL50/4 373 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 374 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 375 128 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 371i 32 ATLS60/80 ATL60/4 ATL50/4 372i 32 ATLS60/80 ATL60/4 ATL50/4 373i(84/100) 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 374i(84/100) 64 ATLS60/80 ATL60/15 ATL60/25 ATL50/15 ATL50/25 128 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 39192 (84) Ultra3900 (3) Target Atmel Gate Array(2) Flash370 Flash370i 375i Note: 9-116 1. Equivalent usable gate data not available. 2. Target array dependent on number of I/O pins used, and pinout. 3. Numbers given in parenthesis indicates optional pin counts. CMOS ASIC ATL60 Series ATL50 CMOS ASIC Atmel FPGAs/PLDs - Cross Reference Table 6 lists the target Gate Arrays for conversion of Atmel FPGAs and PLDs. Table 6. Atmel PLD and FPGA/Atmel Gate Array Cross Reference Atmel PLD/FPGA PLD Equivalent Usable Gates Target Atmel Gate Array(1) I/O Pins ATLS60 Series ATL50 ATF1500 1500 32 ATLS60/80 ATL60/4 ATL50/4 ATV2500 2500 24 ATLS60/80 ATL60/4 ATL50/4 ATV5000 5000 52 ATLS60/80 ATL50/4 ATL60/15 ATL50/4 ATL50/15 ATV5100 5100 52 ATLS60/80 ATL60/4 ATL60/15 ATL50/4 ATL50/15 AT6002 2000-4000 96 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 AT6003 3000-6000 120 ATLS60/120 ATLS60/144 ATL60/60 ATL60/85 ATL50/60 ATL50/85 AT6005 5000-10000 108 ATLS60/100 ATLS60/120 ATL60/40 ATL60/60 ATL50/40 ATL50/60 AT6010 10000-20000 204 ATLS60/208 ATLS60/225 ATL60/200 ATL60/235 ATL50/200 ATL50/235 FPGA Note: ATL60 Series 1. Target array dependent on number of I/O pins used, and pinout. 9-117